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Table 7-9 · Base Address Registers (I/O) 10 Hex to 24 Hex
Bit(s)
0
1
31:2
Bit(s)
0
10:1
31:11
Bit(s)
7:0
31:8
Bit(s)
7:0
31:8
Bit(s)
7:0
15:8
16
17
18
19
110
Type
RO
RO
RW
Type
RO
RO
RW
Type
R
RO
Type
RW
RO
Type
RO
RO
RO
RW
RO
RW
Description
I/O Space Indicator. Set to 1.
Reserved. Set to 0.
Base Address. Depending on the BAR i _ADDR_WIDTH parameter, these bits may be writable or read-only. If a
256-byte address space is set (BAR i _ADDR_WIDTH = 8), bits 31:24 will be readable/writable, and bits 7:2 will be
read-only and set to 0.
Table 7-10 · Expansion ROM Address Register 30 Hex
Description
Expansion ROM enable bit. Set by the EXPR_ENABLE parameter.
Reserved. Set to 0.
Base Address. Depending on the EXPR_ADDR_WIDTH parameter, these bits may be writable or read-only. If a
64 kB address space is set (EXPR_ADDR_WIDTH = 16), bits 31:16 will be readable/writable, and bits 15:11 will be
read-only and set to 0.
Table 7-11 · Capabilities Pointer 34 Hex
Description
For Target-only cores, this will be set to 44 hex. If a Master function is implemented, it will be set to 48 hex or 4C hex.
Reserved. Set to 0.
Table 7-12 · Interrupt Register 3C Hex
Description
Required read/write register. This register has no impact on internal logic.
Set to 01 hex to indicate INTAn.
Table 7-13 · Hot-Swap Capability Register 40 Hex
Description
Hot-swap capability. Set to 06 hex.
Next Capability Pointer. Set to 00 hex.
Device Hiding Arm (DHA)
Since the core only supports programming interface 0, this is '0'.
ENUM# Signal Mask (EIM)
When 1, the HS_ENUMn output is held inactive.
Pending Insert or Extract (PIE)
Set when bit 22 or 23 is set.
LED On/Off (LOO)
v4.0
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